전기전자 아무거나 HOTVHDL로 60초를 표현하는 방법 소스인데,, 어떻게 해야 할까요?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

 

entity clk_60count is
port(clk : in std_logic;
        sec0 : out std_logic_vector(6 downto 0);
        sec1 : out std_logic_vector(6 downto 0));
end clk_60count;

 

architecture sample of clk_60count is
signal count : integer range 0 to 1000000;
signal one : std_logic_vector(3 downto 0);
signal ten : std_logic_vector(3 downto 0);

 

component segment
port(sw : in std_logic_vector(3 downto 0);
        seg : out std_logic_vector(6 downto 0));
end component;

 

for v0,v1 : segment use entity work. segment(sample);

 

begin
    p1 : process(clk)
    begin
        if(clk'event and clk = '1') then
            if(count = 1000000) then
                count <= 0;
            else
                count <= count + 1;
            end if;
        end if;
    end process;
 
 p2 : process(clk)
 begin
  if(clk'event and clk = '1') then
   if(count = 1000000) then
    count <= 0;
   else
    count <= count + 1;
   end if;
  end if;
 end process;
 
 p3 : process(clk)
 begin
  if(clk'event and clk = '1') then
   if(count = 1000000) then
    if(one = "1001") then
     if(ten = "0101") then
      ten <= "0000";
     else
      ten <= ten + 1;
     end if;
    end if;
   end if;
  end if;
 end process;
 
 v0 : segment port map(one,sec0);
 v1 : segment port map(ten,sec1);
 
end sample;

 

60초를 구현하는 소스라더군요. 컴포넌트로 세그먼트를 외부에서 불러올려고 하는데

 

세그먼트는 이렇게 불러와봤는데요.

 

전혀 반응이 없습니다.

 

library ieee;
use ieee.std_logic_1164.all;

entity segment is
port( sw : in std_logic_vector(3 downto 0);
   seg : out std_logic_vector(6 downto 0));
end segment;

architecture sample of segment is
 function dis_7_seg(x : std_logic_vector(3 downto 0)) return std_logic_vector is
  variable seg_decoder : std_logic_vector(6 downto 0);
 begin
  case x is
   when "0000" => seg_decoder := "0111111" ;
   when "0001" => seg_decoder := "0000110" ;
   when "0010" => seg_decoder := "1011011" ;
   when "0011" => seg_decoder := "1001111" ;
   when "0100" => seg_decoder := "1100110" ;
   when "0101" => seg_decoder := "1101101" ;
   when "0110" => seg_decoder := "1111101" ;
   when "0111" => seg_decoder := "0100111" ;
   when "1000" => seg_decoder := "1111111" ;
   when "1001" => seg_decoder := "1100111" ;
   when others => seg_decoder := "0000000" ;
  end case;
 return (seg_decoder);
 end dis_7_seg;
begin
 seg <= dis_7_seg(sw);
end sample;

 

뭐가 뭔지 이해도 잘 안되네요.

 

혹시 책이나,, 레포트 (유료) 괜찮은거 이해잘되는 것 있으면 추천부탁드립니다.